1. Field
Example embodiments of the present invention relate to a nonvolatile memory device using variable resistive elements.
2. Description of the Related Art
Nonvolatile semiconductor memory devices using a resistance material are classified as NOR flash memory devices, NAND flash memory devices, phase change random access memory (PRAM) devices, and others. Whereas, dynamic random access memory (DRAM) devices or flash memory devices write data using charges, phase-change random access memories (PRAMs) store data using a phase-change material, e.g., a chalcogenide alloy, which goes into a crystalline state or an amorphous state due to a change in temperature by cooling followed by heating.
In other words, since the resistance of a phase-change material in the more crystalline state is low and the resistance of an amorphous phase-change material is high, the crystalline state is referred to as a set or “0” state and the amorphous state is referred to as a reset or “1” state. PRAM devices write data by using joule heat, which is generated by applying a set pulse or a reset pulse to a phase change material. In detail, data is written to a PRAM cell either by heating a phase change material of the PRAM cell to higher than its melting point using a reset pulse, and quickly cooling down the phase change material so that the state of the phase change material is changed into an amorphous state, or by heating the phase change material to lower than its crystallization point, maintaining the resulting temperature for a predetermined amount of time, and cooling down the phase change material so that the state of the phase change material is changed into a crystalline phase.
FIGS. 1 and 2 are circuit diagrams for explaining the arrangement of a conventional nonvolatile memory device. For explanatory convenience, FIGS. 1 and 2 show that the conventional nonvolatile memory device includes eight memory banks, but it may contain a different number of memory banks.
Referring to FIG. 1, the conventional nonvolatile memory device includes a plurality of memory banks 10_1 through 10_8, global column select circuits 30_1 through 30_8, global sense amplifier (amp) circuits 40_1 through 40_8, and/or global write driver circuits 50_1 through 50_8. A nonvolatile memory device with higher capacity and higher integration density can be implemented using a hierarchical bit line structure in which a plurality of local bit lines are connected to each of the global bit lines and a hierarchical word line structure in which a plurality of sub word lines are coupled to each of main word lines. As illustrated in FIG. 1, a global bit line GBL is arranged corresponding to each of the plurality of memory banks 10_1 through 10_8. A main word line direction is arranged corresponding to the plurality of memory banks 10_1 through 10_8.
When the global bit line GBL is arranged corresponding to each of the plurality of memory banks 10_1 through 10_8, the conventional nonvolatile memory device has a core architecture as illustrated in FIG. 2. Referring to FIG. 2, a plurality of main word line decoders 20_1 through 20_8 and a plurality of redundancy memory cell arrays 12_1 through 12_8 are arranged corresponding to the plurality of memory banks 10_1 through 10_8.
The conventional nonvolatile memory device having the core architecture illustrated in FIG. 2 requires a considerable increase in the number of sense amps within the global sense amp circuits 40_1 through 40_8 depending on the number of words being pre-fetched during a synchronous burst read operation. For example, if the number of words to be read and pre-fetched from one memory bank (e.g., 10_1) is 4, the number of sense amps needed within one global sense amp circuit (e.g., 40_1) is 64 (1 word (16 bits).times.4). Thus, 512 (64.times.8) sense amps are needed within the 8 global sense amp circuits 40_1 through 40_8. If 8 words are pre-fetched from one memory bank, 1,024 sense amps are needed. If 16 words are pre-fetched from one memory bank, 2,048 sense amps are needed. That is, as the number of words to be pre-fetched increases, the area of the core architecture increases.
It is also difficult to write a large number of bits of data within one memory bank (e.g., 10_1) during a test operation. Assuming that the reset current flowing through one nonvolatile memory cell is about 1 mA when reset data is written to one nonvolatile memory cell, a reset current of about 16 mA may be required to write 16-bits of data into the memory bank 10_1 at a time. That is, because an excessively high level of reset current flows within the memory bank 10_1 (the narrow space), a large number of bits of data are difficult to write at a time. Thus, a large amount of test time is required because a small number of bits of data should be written at a time during a test operation
Still further, the area of the core architecture increases because the plurality of main word line decoders 20_1 through 20_8 are arranged corresponding to the plurality of memory banks 10_1 through 10_8. The area of the core architecture can be further increased because the plurality of redundancy memory cell arrays 12_1 through 12_8 are arranged corresponding to the plurality of memory banks 10_1 through 10_8 because nonvolatile memory cells in the memory banks 10_1 through 10_8 and redundancy memory cells within the redundancy memory cell arrays 12_1 through 12_8 share the same word line WL.